A recurring concern for an integrated circuit memory designer is how to design the memory to operate according to timing specifications across wide variations in operating parameters. The designer must make critical tradeoffs of signal timing in order to simultaneously satisfy two specifications. For example, one important specification is address access time, designated "t.sub.AVQV ", defined as the delay from a valid input address to valid output data during a read cycle. In order to begin the access, an address buffer must present a valid internal address to row and column decoders. Eventually the row and column decoders select one or more memory cells. Minimizing the delay through the address buffer improves T.sub.AVQV.
At the same time, it is necessary to avoid an unintended write to an address location by maintaining the valid internal address for a specified length of time in relation to when a write input signal becomes inactive. This specification is known as write recovery time or "t.sub.WHAX ". In order for the memory to easily interface to other integrated circuits, it is desirable for the t.sub.WHAX specification to be as small as possible. Increasing the delay through the address buffer improves t.sub.WHAX. The actual delay through the address input buffer reflects the tradeoff between t.sub.AVQV and t.sub.WHAX ; the delay is designed to meet both specifications with enough margin at nominal design parameters so that when the actual parameters vary, a large fraction of the integrated circuits manufactured can meet the specifications.
Three types of operating parameters are of particular concern: power supply voltage, temperature, and processing parameters. Integrated circuit memories are typically designed for a nominal power supply voltage of 5.0 volts, with a variation of 10% or more. At lower power supply voltages, complementary metal-oxide-semiconductor (CMOS) and bipolar-CMOS (BICMOS) logic circuits, used in most memories, generally operate slower than at higher power supply voltages. Temperature also affects circuit performance. Integrated circuit memories are typically designed to operate from zero to seventy degrees Celsius. A temperature increases, the resistivity of doped silicon increases, leading to a decrease in switching speed of CMOS and BICMOS circuits. Several processing parameters also affect circuit operation by affecting transistor switching speed. In CMOS and BICMOS integrated circuits, one processing parameter of particular importance is the effective CMOS transistor channel length, known as "L.sub.EFF ". As L.sub.EFF increases, CMOS and BICMOS logic circuits generally become slower.
Faster speed is generally, but not universally, desirable. In the case of the t.sub.AVQV /t.sub.WHAX specifications, faster speed improves t.sub.AVQV but worsens t.sub.WHAX. High voltage and low temperature define a "fast corner", in which the address signals reach the decoders the fastest. At the fast corner, t.sub.AVQV improves over nominal conditions (everything else being equal), but t.sub.WHAX worsens and may even be violated. On the other hand, low voltage and high temperature define a "slow corner", in which the address signals reach the decoders the slowest. At the slow corner, t.sub.WHAX improves over nominal conditions (everything else being equal), but t.sub.AVQV may be violated. When processing parameters vary, it becomes even more difficult to meet the timing specifications. Thus, designing for nominal operating conditions such as 5.0 volts and 25 degrees Celsius is often inadequate to ensure high manufacturing yield.
Known memories improve t.sub.WHAX and similar specifications by adding delays in the input signal paths. The delays change the internal signal timings to optimize the tradeoff between two specifications. As memories become faster, known delay circuits are becoming inadequate to meet the specifications. Since the delay of the delay circuit itself varies with changes in voltage, temperature, and processing, the variability with respect to operating conditions remains. As memories become faster, it is increasingly difficult for the circuit designer to meet more and more stringent timing specifications. The circuit designer needs to be able to design memories which operate according to specification over wide variations in voltage, temperature, and processing.